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<div class="header">
  <div class="summary">
<a href="#groups">API Reference</a> &#124;
<a href="#define-members">Macros</a>  </div>
  <div class="headertitle"><div class="title">DMA (Direct Memory Access)<div class="ingroups"><a class="el" href="group__group__hal__impl.html">CAT1 Implementation Specific</a></div></div></div>
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<a name="details" id="details"></a><h2 class="groupheader">General Description</h2>
<p >DW (DataWire) is one of two DMA hardware implementations for CAT1 (PSoC™ 6). </p>
<p >DW is designed for low latency memory to peripheral or peripheral to memory transfers but can also perform memory to memory transfers and peripheral to peripheral transfers.</p>
<p >DMAC (Direct Memory Access Controller) is the second of two DMA hardware implementations for CAT1 (PSoC™ 6). It is also the implementation that is found on CAT2 (PMG/PSoC™ 4) devices. DMAC is designed with high memory bandwidth for large memory to memory transfers but can perform peripheral to memory, memory to peripheral, and peripheral to peripheral transfers.</p>
<p >Which DMA type is used is dependent on the exact hardware and number of DMA channels already in use. This implementation will attempt to use DMAC first for memory to memory transfers and Datawire otherwise but either type may be used.</p>
<h1><a class="anchor" id="group_hal_impl_dma_interconnect"></a>
Interconnect</h1>
<p >For both DW and DMAC each channel has a single input and a single output trigger available. The input, when triggered, initiates a DMA transfer of the configured type (note that this also affects the type transferred by the SW triggering). For output, a trigger is generated when a DMA transfer of the configured type is completed. For DW and DMAC neither input nor output triggers can be disabled completely but the signals do not, of course, have to be connected through the interconnect.</p>
<h1><a class="anchor" id="section_hal_impl_dma_data_arr_requirement"></a>
User-provided data arrays requirements</h1>
<p >CM7 cores in CAT1C devices support Data Cache. Data Cache line is 32 bytes. User needs to make sure that the source and destination buffer pointers points to 32 byte aligned data. User can use CY_ALIGN(32) macro for 32 byte alignment. </p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="groups" name="groups"></a>
API Reference</h2></td></tr>
<tr class="memitem:group__group__hal__impl__dma__dmac"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__impl__dma__dmac.html">DMAC (Direct Memory Access Controller)</a></td></tr>
<tr class="memdesc:group__group__hal__impl__dma__dmac"><td class="mdescLeft">&#160;</td><td class="mdescRight">Implementation specific interface for using the DMAC DMA peripheral. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:group__group__hal__impl__dma__dw"><td class="memItemLeft" align="right" valign="top">&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__group__hal__impl__dma__dw.html">DW (Datawire)</a></td></tr>
<tr class="memdesc:group__group__hal__impl__dma__dw"><td class="mdescLeft">&#160;</td><td class="mdescRight">Implementation specific interface for using the Datawire DMA peripheral. <br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga81946da56dd6ba8afd28f6056b1d779a"><td class="memItemLeft" align="right" valign="top"><a id="ga81946da56dd6ba8afd28f6056b1d779a" name="ga81946da56dd6ba8afd28f6056b1d779a"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CYHAL_DMA_PRIORITY_DEFAULT</b>&#160;&#160;&#160;<a class="el" href="group__group__hal__impl__dma.html#ga30998fd4febd3080e00922f969b08712">CYHAL_DMA_PRIORITY_LOW</a></td></tr>
<tr class="memdesc:ga81946da56dd6ba8afd28f6056b1d779a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Default DMA channel priority. <br /></td></tr>
<tr class="separator:ga81946da56dd6ba8afd28f6056b1d779a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaca50872208f80fb4625591afbaf79d70"><td class="memItemLeft" align="right" valign="top"><a id="gaca50872208f80fb4625591afbaf79d70" name="gaca50872208f80fb4625591afbaf79d70"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CYHAL_DMA_PRIORITY_HIGH</b>&#160;&#160;&#160;0</td></tr>
<tr class="memdesc:gaca50872208f80fb4625591afbaf79d70"><td class="mdescLeft">&#160;</td><td class="mdescRight">High DMA channel priority. <br /></td></tr>
<tr class="separator:gaca50872208f80fb4625591afbaf79d70"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0b9bf793bb1892836a901599c26fd698"><td class="memItemLeft" align="right" valign="top"><a id="ga0b9bf793bb1892836a901599c26fd698" name="ga0b9bf793bb1892836a901599c26fd698"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CYHAL_DMA_PRIORITY_MEDIUM</b>&#160;&#160;&#160;1</td></tr>
<tr class="memdesc:ga0b9bf793bb1892836a901599c26fd698"><td class="mdescLeft">&#160;</td><td class="mdescRight">Medium DMA channel priority. <br /></td></tr>
<tr class="separator:ga0b9bf793bb1892836a901599c26fd698"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga30998fd4febd3080e00922f969b08712"><td class="memItemLeft" align="right" valign="top"><a id="ga30998fd4febd3080e00922f969b08712" name="ga30998fd4febd3080e00922f969b08712"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>CYHAL_DMA_PRIORITY_LOW</b>&#160;&#160;&#160;3</td></tr>
<tr class="memdesc:ga30998fd4febd3080e00922f969b08712"><td class="mdescLeft">&#160;</td><td class="mdescRight">Low DMA channel priority. <br /></td></tr>
<tr class="separator:ga30998fd4febd3080e00922f969b08712"><td class="memSeparator" colspan="2">&#160;</td></tr>
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